The degree of integration of semiconductor integrated circuit devices has been increasing. Reductions in size have been achieved in accordance with a scaling rule. As for an in-plane basic dimension, techniques complying with the 90 nm rule and the 65 nm rule have already become established. The 32 nm rule has been developed and its limit is being approached.
In recent years, the integration of semiconductor microchips has shifted from two-dimensional integration in which the degree of in-plane integration is increased to three-dimensional integration in which a plurality of chips are vertically laminated. Chips contained in cellular phones are mainly formed by the system-in-package technique. Devices in which chips are laminated such as flash memories have been released in countries other than Japan. There has been a trend that such three-dimensional integration techniques are further growing in use. Production of devices by three-dimensional integration techniques requires a process of laminating wafers and chips (collectively referred to as substrates) and a process of electrically connecting the laminated substrates.
A process of bonding substrates to each other, the substrates including semiconductor integrated circuits in which semiconductor devices such as MOS transistors are integrated, is desirably conducted at a temperature at which the distribution of dopants in the semiconductor devices is not changed.
Japanese Laid-open Patent Publication No. 10-275752 discusses that methods of forming bonded wafers such as a direct bonding method, an electrostatic bonding method, and a soot glass bonding method require a bonding temperature of more than 1000° C., a bonding period of several hours to several tens of hours, and a large heat-treatment furnace. Japanese Laid-open Patent Publication No. 10-275752 discusses that at least two wafers be bonded to each other with a noncrystalline aromatic polyimide monolayer or an aromatic polyimide member in which a noncrystalline aromatic polyimide layer is formed on each surface of a base polyimide layer.
Japanese Laid-open Patent Publication No. 2001-326326 discusses that the following formation of substrate-through-via electrical conductors. When device isolation regions of the shallow trench isolation (STI) type are formed in a substrate, some of the device isolation regions are made deeper than the other device isolation regions. Deep trenches are formed in the deep device isolation regions and wiring grooves that are to be filled with a first wiring layer are subsequently formed. The trenches and the wiring grooves are filled with the wiring layer to provide an integrated circuit device. After that, the back surface of the substrate is ground and polished to thereby expose the wiring embedded in the deep device isolation regions and form substrate-through-via electrical conductors.